Delay Modelling for Buffered RLC/RLY Trees
نویسندگان
چکیده
For deep-submicron, high-performance circuits, the inductive effect plays a very important role in determining the circuit delay. In this paper, we derive accurate formulae for modeling the delays of buffered RLY/RLC wires and trees. Our formulae can handle balanced and un-balanced trees and consider buffer insertion. Extensive simulations with HSPICE show that the formulae have high fidelity, with an average error of within 5.51% based on the 180 nm technology. The simulations show that our formulae are more accurate than previous works.
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تاریخ انتشار 2004